Motorola CPU32 Reference Manual page 235

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ROXL, ROXR (Memory)
15
14
13
1
1
1
dr Field: 0 = Right 1 = Left
ROL, ROR (Memory)
15
14
13
1
1
1
dr Field: 0 = Right 1 = Left
LPSTOP
15
14
13
1
1
1
0
0
0
TBLU, TBLUN (Data Register Interpolate)
15
14
13
1
1
1
REGISTER Dx
R Field: 0 = Unrounded 1 = Rounded
TBLU, TBLUN (Lookup and Interpolate)
15
14
13
1
1
1
0
REGISTER Dx
R Field: 0 = Unrounded 1 = Rounded
TBLS, TBLSN (Data Register Interpolate)
15
14
13
1
1
1
REGISTER Dx
R Field: 0 = Unrounded 1 = Rounded
TBLS, TBLSN (Lookup and Interpolate)
15
14
13
1
1
1
0
REGISTER Dx
R Field: 0 = Unrounded 1 = Rounded
CPU32
REFERENCE MANUAL
12
11
10
9
0
0
1
0
12
11
10
9
0
0
1
1
12
11
10
9
1
1
0
0
0
0
0
0
IMMEDIATE DATA
12
11
10
9
1
1
0
0
0
R
0
12
11
10
9
1
1
0
0
0
R
0
12
11
10
9
1
1
0
0
1
R
0
12
11
10
9
1
1
0
0
1
R
0
INSTRUCTION SET
8
7
6
5
dr
1
1
8
7
6
5
dr
1
1
8
7
6
5
0
0
0
0
1
1
1
0
8
7
6
5
0
0
0
0
0
SIZE
0
8
7
6
5
0
0
0
1
SIZE
0
8
7
6
5
0
0
0
0
0
SIZE
0
8
7
6
5
0
0
0
1
SIZE
0
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
4
3
2
1
0
0
0
0
0
0
0
0
4
3
2
1
0
0
REGISTER Dym
0
0
REGISTER Dyn
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
4
3
2
1
0
0
REGISTER Dym
0
0
REGISTER Dyn
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
MOTOROLA
0
0
0
0
0
0
0
0
0
0
0
4-187

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