Epson S1C31D50 Technical Instructions page 110

7.7.10. P9 Port Group
The P9 port group consists of seven ports P90–P95 and they support the GPIO and interrupt functions.
Register name Bit
PPORTP9DAT 15-14
(P9 Port Data Register) 13–8
7–6
5–0
PPORTP9IOEN 15-14
(P9 Port Enable
13–8
Register)
7–6
5–0
PPORTP9RCTL 15-14
(P9 Port Pull-up/down
13–8
Control Register)
7–6
5–0
PPORTP9INTF 15–8
(P9 Port Interrupt Flag 7–6
Register)
5–0
PPORTP9INTCTL 15-14
(P9 Port Interrupt 13–8
Control Register)
7–6
5–0
PPORTP9CHATEN 15–8
(P5 Port Chattering 7–6
Filter Enable Register)
5–0
PPORTP9MODSEL 15–8
(P9 Port Mode Select 7–6
Register)
5–0
PPORTP9FNCSEL 15–14
(P9 Port Function 13–12
Select Register)
11–10
9–8
7–6
5–4
3–2
1–0
P5SELy = 0
Port
name GPIO
Peripheral
P90 P90 QSPI Ch.0
P91 P91 QSPI Ch.0
P92 P92 QSPI Ch.0
P93 P93 QSPI Ch.0
P94 P94 QSPI Ch.0
P95 P95 QSPI Ch.0
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 7.7.10.1 Control Registers for P9 Port Group
Bit name Initial
–
P9OUT[5:0] 0x00
–
P9IN[5:0] 0x00
–
P9IEN[5:0] 0x00
–
P9OEN[5:0] 0x00
–
P9PDPU[5:0] 0x00
–
P9REN[5:0] 0x00
– 0x00
–
P9IF[5:0] 0x00
–
P9EDGE[5:0] 0x00
–
P9IE[5:0] 0x00
– 0x00
–
P9CHATEN[5:0] 0x00
– 0x00
–
P9SEL[5:0] 0x00
–
–
P95MUX[1:0]
P94MUX[1:0]
P93MUX[1:0]
P92MUX[1:0]
P91MUX[1:0]
P90MUX[1:0]
Table 7.7.10.2 P9 Port Group Function Assignment
P9yMUX = 0x0 P9yMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral
QSPICLK0 –
QSDIO00 –
QSDIO01 –
QSDIO02 –
QSDIO03 –
#QSPISS0 –
Seiko Epson Corporation
Reset R/W
0 – R
H0 R/W
0 – R
H0 R
0 – R
H0 R/W
0 – R
H0 R/W
0 – R
H0 R/W
0 – R
H0 R/W
– R
0 – R
H0 R/W
0 – R
H0 R/W
0 – R
H0 R/W
– R
0 – R
H0 R/W
– R
0 – R
H0 R/W
0x0 – R
0x0 – R
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
P5SELy = 1
P9yMUX = 0x2
(Function 2)
Pin Peripheral
– –
– –
– –
– –
– –
– –
Remarks
–
–
–
–
Cleared by writing 1.
–
–
–
–
P9yMUX = 0x3
(Function 3)
Pin Peripheral Pin
– – –
– – –
– – –
– – –
– – –
– – –
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