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7.2.4. CMOS Output and High Impedance State
The I/O cells except for analog output can output signals in the V
may be put into high-impedance (Hi-Z) state.
7.3. Clock Settings
7.3.1. PPORT Operating Clock
When using the chattering filter for entering external signals to PPORT, the PPORT operating clock
CLK_PPORT must be supplied to PPORT from the clock generator.
The CLK_PPORT supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the
"Power Supply, Reset, and Clocks" chapter).
2. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
3. Set the following PPORTCLK register bits:
PPORTCLK.CLKSRC[1:0] bits
-
PPORTCLK.CLKDIV[3:0] bits (Clock division ratio selection = Clock frequency setting)
-
4.
Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
Settings in Step 3 determine the input sampling time of the chattering filter.
7.3.2. Clock Supply in SLEEP Mode
When using the chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT
must be configured so that it will keep suppling by writing 0 to the CLGOSC.xxxxSLPC bit for the
CLK_PPORT clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source is 1, the CLK_PPORT clock source is
deactivated during SLEEP mode and it disables the chattering filter function regardless of the
PPORTPxCHATEN.Px- CHATENy bit setting (chattering filter enabled/disabled).
7.3.3. Clock Supply During Debugging
The CLK_PPORT supply during debugging should be controlled using the PPORTCLK.DBRUN bit.
The CLK_PPORT supply to PPORT is suspended when the CPU enters debug state if the
PPORTCLK.DBRUN bit = 0. After the CPU returns to normal operation, the CLK_PPORT supply resumes.
The PPORT chattering filter stops operating when the CLK_PPORT supply is suspended. If the chattering
filter is enabled in PPORT, the input port function is also deactivated. However, the control registers can
be altered. If the PPORTCLK.DBRUN bit = 1, the CLK_PPORT supply is not suspended and the chattering
filter will keep operating in a debug state.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
DD
(Clock source selection)
Seiko Epson Corporation
and V
levels. Also the GPIO ports
SS
7-3
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