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9.3. Operations
9.3.1. WDT2 Control
Activating WDT2
WDT2 should be initialized and started up with the procedure listed below.
1.
Write 0x0096 to the MSCPROT.PROT[15:0] bits.
2.
Configure the WDT2 operating clock.
3.
Set the WDT2CTL.MOD[1:0] bits.
4.
Set the WDT2CMP.CMP[9:0] bits.
5.
Write 1 to the WDT2CTL.WDTCNTRST bit.
6.
Write a value other than 0xa to the WDT2CTL.WDTRUN[3:0] bits.
7.
Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
NMI/reset generation cycle
Use the following equation to calculate the WDT2 NMI/reset generation cycle.
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Where
t
:
NMI/reset generation cycle [second]
WDT
CLK_WDT2:
CMP:
Setting value of the WDT2CMP.CMP[9:0] bits
t
Example)
= 2.5 seconds when CLK_WDT2 = 256 Hz and the WDT2CMP.CMP[9:0] bits = 639
WDT
Resetting WDT2 counter
To prevent an unexpected NMI/reset to be generated by WDT2, its embedded counter must be reset
periodically via software while WDT2 is running.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits.
2. Write 1 to the WDT2CTL.WDTCNTRST bit.
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits.
A location should be provided for periodically processing this routine. Process this routine within
the t
cycle. After resetting, WDT2 starts counting with a new NMI/reset generation cycle.
WDT
Occurrence of counter compare match
If WDT2 is not reset within the tWDT cycle for any reason and the counter reaches the setting value
of the WDT2CMP.CMP[9:0] bits, a compare match occurs to cause WDT2 to issue an NMI or reset
according to the setting of the WDT2CTL.MOD[1:0] bits.
If an NMI is issued, the WDT2CTL.STATNMI bit is set to 1. This bit can be cleared to 0 by writing 1 to
the WDT2CTL.WDTCNTRST bit. Be sure to clear the WDT2CTL.STATNMI bit in the NMI handler
routine,
If a compare match occurs, the counter is automatically reset to 0 and it continues counting.
Deactivating WDT2
WDT2 should be stopped with the procedure listed below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits.
2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits.
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
9-2
(����. 9.1)
WDT2 operating clock frequency [Hz]
Seiko Epson Corporation
(Remove system protection)
(Select WDT2 operating mode)
(Set NMI/reset generation cycle)
(Reset WDT2 counter)
(Start up WDT2)
(Remove system protection)
(Reset WDT2 counter)
(Set system protection)
(Remove system protection)
(Stop WDT2)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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