Advertisement
19.5. Interrupts
The ADC12A has a function to generate the interrupts shown in Table 19.5.1.
Interrupt
Analog input signal m A/D
conversion completion
A/D conversion result
over- write error
Note that the A/D conversion continues even if an A/D conversion result overwrite error has occurred.
A/D conversion result overwrite errors are decided regardless of whether the ADC12A_nADD register has
been read or not.
The ADC12A provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is
sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt
enable bit, is set. For more information on interrupt control, refer to the "Interrupt" chapter.
19.6. DMA Transfer Requests
The ADC12A has a function to generate DMA transfer requests from the causes shown in Table 19.6.1.
Cause to request DMA
transfer
Analog input signal m
A/D conversion
completion
The ADC12A provides DMA transfer request enable bits corresponding to each DMA transfer request
flag shown above for the number of DMA channels. A DMA transfer request is sent to the pertinent
channel of the DMA controller only when the DMA transfer request flag, of which DMA transfer has
been enabled by the DMA transfer request enable bit, is set. The DMA transfer request flag also serves
as an interrupt flag, therefore, both the DMA transfer request and the interrupt cannot be enabled at
the same time. After a DMA transfer has completed, disable the DMA transfer to prevent unintended
DMA transfer requests from being issued. For more information on the DMA control, refer to the
"DMA Controller" chapter.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 19.5.1 ADC12A Interrupt Function
Interrupt flag
ADC12A_nINTF.ADmCIF
ADC12A_nINTF.OVIF
Table 19.6.1 DMA Transfer Request Causes of ADC12A
DMA transfer request flag
A/D conversion completion
flag (ADC12A_nINTF.ADmCIF)
Seiko Epson Corporation
Set condition
When an analog input signal m A/D conver
-sion
result
is
loaded
ADC12A_nADD register
When a new A/D conversion result is
loaded to the ADC12A_nADD register while
the ADC12A_nINTF.ADmCIF bit = 1
Set condition
When an analog input signal m
A/ D conversion result is loaded
to the ADC12A_nADD register
Clear
condition
Writing 1
to
the
Writing 1
Clear
condition
When the
DMA transfer
request is
accepted
19-7
Advertisement
