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DMAC Configuration Register
Register name
Bit
DMACCFG
31–24
23–16
15–8
7–1
0
Bits 31–1
Reserved
Bit 0
MSTEN
This bit enables the DMA controller.
1 (W): Enable
0 (W): Disable
DMAC Control Data Base Pointer Register
Register name
Bit
DMACCPTR
31–0
Bits 31–0
CPTR[31:0]
These bits set the leading address of the data structure.
Depending on the number of channels implemented, low-order bits are configured for read
only.
Table 6.8.2 CPTR Writable/Read-Only Bits Depending On Number of Channel Implemented
Number of channel
DMAC Alternate Control Data Base Pointer Register
Register name
Bit
DMACACPTR
31–0
Bits 31–0
ACPTR[31:0]
These bits show the alternate data structure base address.
DMAC Software Request Register
Register name
Bit
DMACSWREQ
31–0
Bits 31–0
SWREQ [31:0]
These bits issue a software DMA transfer request to each channel.
1 (W): Issue a software DMA transfer request
0 (W): Ineffective
Each bit corresponds to a DMAC channel (e.g. bit n corresponds to Ch.n). The high-order
bits for the unimplemented channels are ineffective.
6-14
Bit name
Initial
–
0x00
–
0x00
–
0x00
–
0x00
MSTEN
–
Bit name
Initial
CPTR[31:0]
0x0000
0000
Writable bits
implemented
1
CPTR[31:5]
2
CPTR[31:6]
3–4
CPTR[31:7]
5–8
CPTR[31:8]
9–16
CPTR[31:9]
17–32
CPTR[31:10]
Bit name
Initial
ACPTR[31:0]
–
Bit name
Initial
SWREQ[31:0]
–
Seiko Epson Corporation
Reset
R/W
–
R
–
–
R
–
R
–
–
R
–
W
Reset
R/W
H0
R/W
–
Read-only bits
CPTR[4:0]
CPTR[5:0]
CPTR[6:0]
CPTR[7:0]
CPTR[8:0]
CPTR[9:0]
Reset
R/W
H0
R
Reset
R/W
–
W
Remarks
Remarks
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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