Epson S1C31D50 Technical Instructions page 375

HW Processor Command Trigger Register
Register name Bit
HWPCMDTRG 15–1
0
Bits 15–1 Reserved
Bit 0 HWP0TRG
This bit indicates the HW Processor command trigger.
1 (R):
0 (R):
1(W):
0(W):
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name Initial
– 0x00
HWP0TRG 0x0
Setting in progress
Ready to set the command trigger
Set the command trigger
Setting prohibited
Seiko Epson Corporation
Reset R/W
– R
H0 R/W
Remarks
–
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