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17.7. Control Registers
T16B Ch.n Clock Control Register
Register name
Bit
T16B_nCLK
15–9
8
7–4
3
2–0
Bits 15–9
Reserved
Bit 8
DBRUN
This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not.
1 (R/W):
0 (R/W):
Bits 7–4
CLKDIV[3:0]
These bits select the division ratio of the T16B Ch.n operating clock (counter clock).
Bit 3
Reserved
Bits 2–0
CLKSRC[2:0]
These bits select the clock source of T16B Ch.n.
T16B_nCLK.
CLKDIV[3:0] bits
IOSC
0xf
1/32,768
0xe
1/16,384
0xd
1/8,192
0xc
1/4,096
0xb
1/2,048
0xa
1/1,024
0x9
1/512
0x8
1/256
0x7
1/128
0x6
1/64
0x5
1/32
0x4
1/16
0x3
0x2
0x1
0x0
(Note) The oscillator circuits/external inputs that are not supported in this IC cannot be selected as the clock source.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
DBRUN
CLKDIV[3:0]
–
CLKSRC[2:0]
Clock supplied during debugging
No clock supplied during debugging
Table 17.7.1 Clock Source and Division Ratio Settings
0x0
0x1
0x2
OSC1
OSC3
1/32,768
1/16,384
1/8,192
1/1
1/4,096
1/2,048
1/1,024
1/512
1/256
1/256
1/128
1/128
1/64
1/64
1/32
1/32
1/16
1/16
1/8
1/8
1/8
1/4
1/4
1/4
1/2
1/2
1/2
1/1
1/1
1/1
Seiko Epson Corporation
Reset
R/W
–
R
0
H0
R/W
0x0
H0
R/W
0
–
R
0x0
H0
R/W
T16B_nCLK.CLKSRC[2:0] bits
0x3
0x4
EXOSC
EXCLn0
1/1
1/1
Remarks
–
0x5
0x6
0x7
EXCLn0
EXCLn1
inverted
inverted
EXCLn1
input
input
1/1
1/1
1/1
17-25
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