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Table 10.3.2.1 lists the frequency tolerance correction rates when the theoretical regulation execution
cycle time n is 4,096 seconds as an example.
Table 10.3.2.1 Correction Rates when Theoretical Regulation Execution Cycle Time n = 4,096 Seconds
RTCACTLH.RTCTRM[6:0]
bits (two's-complement)
0x00
0x01
0x02
0x03
· · ·
0x3e
0x3f
Notes:
•
The theoretical regulation affects only the real-time clock counter and 1 Hz counter. It does
•
not affect the stopwatch counter.
•
After a value is written to the RTCACTLH.RTCTRM[6:0] bits, the theoretical regulation cor-
rection takes effect on the 1 Hz counter value at the same timing as when the 1 Hz counter
changes to 0x7f. Also an interrupt occurs depending on the counter value at this time.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Correction
Correction rate
value (decimal)
[ppm]
0
0.0
1
1.0
2
1.9
3
2.9
· · ·
· · ·
62
59.1
63
60.1
Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm
Seiko Epson Corporation
RTCACTLH.RTCTRM[6:0]
bits (two's-complement)
value (decimal)
0x40
0x41
0x42
0x43
· · ·
0x7e
0x7f
Correction
Correction rate
[ppm]
-64
-61.0
-63
-60.1
-62
-59.1
-61
-58.2
· · ·
· · ·
-2
-1.9
-1
-1.0
10-3
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