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CLG Interrupt Enable Register
Register name
Bit
CLGINTE
15–9
8
7
6
5
4
3
2
1
0
Bits 15–9, 7, 6, 3
Bit 8
OSC3TERIE
Bit 5
OSC1STPIE
Bit 4
OSC3TEDIE
Bit 2
OSC3STAIE
Bit 1
OSC1STAIE
Bit 0
IOSCSTAIE
These bits enable the OSC1 oscillation stop and OSC3 oscillation auto-trimming
completion interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the interrupt as follows:
CLGINTE.OSC3TERIE bit: OSC3 oscillation auto-trimming error interrupt
CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt
CLGINTE.OSC3TEDIE bit: OSC3 oscillation auto-trimming completion interrupt
CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
OSC3TERIE
0
–
0
–
0
OSC1STPIE
0
OSC3TEDIE
0
–
0
OSC3STAIE
0
OSC1STAIE
0
IOSCSTAIE
0
Reserved
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
–
R
–
R
H0
R/W
H0
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
Remarks
–
2-29
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