Advertisement
2
16. I
C (I2C)
16.1. Overview
The I2C is a subset of the I
•
Functions as an I
•
Supports Bold mode (up to 100 kbit/s) and fast mode (up to 400 kbit/s).
•
Supports 7-bit and 10-bit address modes.
•
Supports clock stretching.
•
Includes a baud rate generator for generating the clock in master mode.
•
No clock source is required to run the I2C in slave mode, as it can run with the I
•
Slave mode is capable of being operated in SLEEP mode allowing wake-up by an interrupt
when an address match is detected.
•
Master mode supports automatic bus clear sending function.
•
Can generate receive buffer full, transmit buffer empty, and other interrupts.
•
Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs.
Figure 16.1.1 shows the I2C configuration.
Item
Number of channels
I2C Ch.n
DMA
controller
TBEDMAEN
RBFDMAEN
CPU core
BYTEENDIE
GCIE
NACKIE
STOPIE
STARTIE
ERRIE
RBFIE
TBEIE
SFTRST
OADR10
OADR[9:0]
GCEN
MST
TXNACK
TXSTART
TXSTOP
CLKSRC[1:0]
CLKDIV[1:0]
Clock
DBRUN
generator
MODEN
CLK_I2C
n
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
C bus interface. The features of the I2C are listed below.
2
C bus master (single master) or a slave device.
2
Table 16.1.1 I2C Channel Configuration of S1C31D50
3 channels (Ch.0 ,Ch.1 and Ch.2)
Receive data buffer
DMA request
control circuit
x
x
BYTEENDIF
Interrupt
control
circuit
Transmit/receive
BRT[6:0]
Figure 16.1.1 I2C Configuration
Seiko Epson Corporation
S1C31D50
Shift register
RXD[7:0]
Transmit data
buffer
Shift register
TXD[7:0]
GCIF
NACKIF
STOPIF
STARTIF
ERRIF
RBFIF
TBEIF
control circuit
Slave mode
controller
SDALOW
SCLLOW
Master mode
controller
Baud rate
generator
C bus signals only.
2
SDAn
V
SS
BSY
TR
SCLn
SCLO
V
SS
16-1
Advertisement
