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21.5.9. Memory Check Error
Once an ERROR is occurred, HW Processor makes an interrupt, please check ERROR register in "21.5.11.
Memory Check Function Registers".
Figure 21.5.9.1 shows "Memory Check Error" check flow..
21.5.10.
Memory Check Interrupt Masking
In the "Memory Check" function, the interrupt occurs when the state transitions.
This interrupt can be masked by enabling the bit of INTMASK register in "21.5.11. Memory Check
Function Registers".
The mask bits are listed below.
INTMASK.TO_IDLE bit
When this bit is enabled, the interrupt is generated when the state moves to "mc_state_idle" is
masked.
INTMASK.TO_PROCESSING bit
When this bit is enabled, the interrupt is generated when the state moves to "mc_state_ram_rw",
"mc_state_ram_march_c", "mc_state_checksum" or "mc_state_crc" is masked.
Figure 21.5.10.1 shows "Memory Check Interrupt Masking" flow.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Wait HWPINTF.HWP1IF = 1(means Error occurred)
Check ERROR Register
Figure 21.5.9.1 "Memory Check Error" Check Flow.
Wait STATE_x = "mc_state_idle"
Wait STATUS.READY = mc_status_ready
Set INTMASK to 0x000x
Figure 21.5.10.1 "Memory Check Interrupt Masking" Flow
Seiko Epson Corporation
HW Processor interrupts to cortex
21-33
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