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2.2.3. Reset Sources
The reset source refers to causes that request system initialization. The following shows the reset
sources.
#RESET pin
Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request.
POR and BOR
POR (Power On Reset) issues a reset request when the rise of V
Reset) issues a reset request when a certain V
circuits ensure that the system will be reset properly when the power is turned on and the supply
voltage is out of the operating voltage range. Figure 2.2.3.1 shows an example of POR and BOR
internal reset operation according to variations in V
V
DD
V
SS
Internal state
X
VRST-: Reset detection voltage VRST+: Reset canceling voltage
X
For the POR and BOR electrical specifications, refer to "POR/BOR characteristics" in the "Electrical
Characteristics" chapter.
Reset request from the CPU
The CPU issues a reset request by writing 1 to the AIRCR.SYSRESETREQ bit in the system control
register. For more information, refer to the "Cortex
Key-entry reset
Inputting a low level signal of a certain period to the I/O port pins configured to a reset input issues
a reset re- quest. This function must be enabled using an I/O port register. For more information,
refer to the "I/O Ports" chapter.
Watchdog timer reset
Setting the watchdog timer into reset mode will issue a reset request when the counter overflows.
This helps re- turn the runaway CPU to a normal operating state. For more information, refer to the
"Watchdog timer" chapter.
Supply voltage detector reset
By enabling the low power supply voltage detection reset function, the supply voltage detector will
issue a reset request when a drop in the power supply voltage is detected. This makes it possible to
put the system into reset state if the IC must be stopped under a low voltage condition. For more
information, refer to the "Supply Volt- age Detector" chapter.
Peripheral circuit software reset
Some peripheral circuits provide a control bit for software reset (MODEN or SFTRST). Setting this bit
initializes the peripheral circuit control bits. Note, however, that the software reset operations
depend on the peripheral circuit. For more information, refer to "Control Registers" in each
peripheral circuit chapter.
Note:
The MODEN bit of some peripheral circuits does not issue software reset.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
V
V
RST-
RST-
RST
RUN
Indefinite (operating limit)
Figure 2.2.3.1 Example of Internal Reset by POR and BOR
Seiko Epson Corporation
is detected. BOR (Brown-out
DD
voltage level is detected. Reset requests from these
DD
.
DD
V
RST+
V
RST-
RST
RUN
RST
RESET state
RST
-M0+ Technical Reference Manual."
®
V
RST+
X
RST
RUN
CPU RUN state
RUN
X
2-5
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