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START condition interrupt
(1)
Master mode
SDA
SCL
Slave mode
SDA
SCL
BSY = 1
STOP condition interru
(2)
Master mode
SDA
SCL
Slave mode
SDA
SCL
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
BRT + 3
fCLK_I2Cn
TXSTART = 1
Address matching the I2C_nOADR register
1
2
pt Master mode
(BRT + 3) × 3
fCLK_I2Cn
TXSTOP = 1
RXD[7:0] read (during reception)
BSY = 0
STOPIF = 1
Figure 16.5.1 START/STOP Condition Interrupt Timings
Seiko Epson Corporation
TXSTART = 0
STARTIF = 1
R/W
ACK
7
8
9
STARTIF = 1
TR = 0/1
TXSTOP = 0
STOPIF = 1
16-19
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