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Epson S1C31D50 Technical Instructions page 426

Cmos 32-bit single chip microcontroller
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QSPI_0RBFDMAEN
(QSPI Ch.0
0x0020
Receive Buffer Full
069e
DMA Request
Enable Register)
QSPI_0FRLDMAEN
(QSPI Ch.0 FIFO
0x0020
Data
06a0
Ready DMA
Request Enable
Register)
QSPI_0MMACFG1
(QSPI Ch.0
0x0020
Memory Mapped
06a2
Access Con-
figuration Register
1)
QSPI_0RMADRH
(QSPI Ch.0
0x0020
Remap- ping Start
06a4
Address High
Register)
QSPI_0MMACFG2
(QSPI Ch.0
0x0020
Memory Mapped
06a6
Access Con-
figuration Register
2)
QSPI_0MB
0x0020
(QSPI Ch.0 Mode
06a8
Byte Register)
B-48
15–8
7–4
3–0
RBFDMAEN[3:0]
15–8
7–4
3–0
FRLDMAEN[3:0]
15–8
7–4
3–0
TCSH[3:0]
15–4
RMADR[31:20]
3-0
15–12
DUMDL[3:0]
11–8
DUMLN[3:0]
7–6
DATTMOD[1:0]
5–4
DUMTMOD[1:0]
3–2
ADRTMOD[1:0]
1
ADRCYC
0
MMAEN
15–8
XIPACT[7:0]
7–0
XIPEXT[7:0]
Seiko Epson Corporation
0x00
R
0x0
R
0x0
H0
R/W
0x00
R
0x0
R
0x0
H0
R/W
0x00
R
0x0
R
0x0
H0
R/W
0x000
H0
R/W
0x0
R
0x0
H0
R/W
0x0
H0
R/W
0x0
H0
R/W
0x0
H0
R/W
0x0
H0
R/W
0
H0
R/W
0
H0
R/W
0x00
H0
R/W
0x00
H0
R/W
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)

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