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QSPI Ch.n Interrupt Flag Register
Register name
Bit
QSPI_nINTF
15–8
7
6
5–4
3
2
1
0
Bits 15–8
Reserved
Bit 7
BSY
This bit indicates the QSPI operating status.
1 (R): Transmit/receive busy
0 (R): Idle
Bit 6
MMABSY
This bit indicates the QSPI memory mapped access operating status.
1 (R): Memory mapped access state machine busy
0 (R): Idle
Bits 5–4
Reserved
Bit 3
OEIF
Bit 2
TENDIF
Bit 1
RBFIF
Bit 0
TBEIF
These bits indicate the QSPI interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag (OEIF, TENDIF)
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
QSPI_nINTF.OEIF bit:
QSPI_nINTF.TENDIF bit: End-of-transmission interrupt
QSPI_nINTF.RBFIF bit:
QSPI_nINTF.TBEIF bit:
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
BSY
0
MMABSY
0
–
0x0
OEIF
0
TENDIF
0
RBFIF
0
TBEIF
1
Overrun error interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Seiko Epson Corporation
Reset
R/W
–
R
H0
R
H0
R
–
R
H0/S0
R/W
Cleared by writing 1.
H0/S0
R/W
H0/S0
R
Cleared by reading the QSPI_nRXD
register.
H0/S0
R
Cleared by writing to the
QSPI_nTXD register.
Remarks
–
15-37
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