Advertisement
CS#
0
1
2
SCLK
Instruction
IO0
7
6
5
IO1
IO2
IO3
Figure 15.5.2.1 XIP Example - Spansion S25FL128S Quad I/O Read Command Sequence
CS#
SCLK
2 cycles
Data N
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Figure 15.5.2.2 XIP Example - Spansion S25FL128S Continuous Quad I/O Read Command Sequence
In memory mapped access mode, the QSPI automates toggling of the slave select signal and
executing address, dummy, and data cycles so that the CPU will be able to read the external Flash
memory mapped to the system memory area. This further reduces CPU overhead.
The transfer mode can be configured for address, dummy, and data cycles individually. The address
cycle supports 24 and 32-bit addresses. The QSPI considers that the mode cycle (or XIP
activation/termination confirmation) is a part of the dummy cycle, so a mode cycle is sent out on the I/O
data line in a dummy cycle.
The 1M-byte system memory area starting at address 0x80000 is used to map the external Flash memory
and to access from the CPU. Up to 4G-byte Flash memory can be accessed from this area using a
remapping register. Once the external Flash memory is set into XIP mode and a read command is sent
in register access mode, the CPU can directly read external Flash memory data through this area. When
a read access to a non-sequential address occurs in memory mapped access mode, the QSPI
automatically executes a new address and dummy cycles. When memory mapped access mode is
disabled by setting a register, the QSPI executes an address cycle and a dummy cycle including a mode
byte that specifies to terminate XIP mode.
Memory mapped access mode supports 8, 16, and 32-bit read accesses.
The 32-bit access is mainly used to read data in a large memory block sequentially. In this access, up
to two 32- bit data are prefetched into the internal FIFO. Therefore, zero-wait read access is possible if
the desired data has already been fetched in the FIFO.
The 8 and 16-bit accesses are mainly used to read data in a small memory block or to read data from
non-sequential addresses. Prefetching is not performed as it is unnecessary in non-sequential read.
Therefore, overhead of a couple of clocks occurs between accesses.
The QSPI allows incorporating 8 and 16-bit accesses into 32- bit accesses. Prefetching data into FIFO is
only per- formed immediately after a 32-bit read. An 8 or 16-bit read at the sequential address after a
32-bit read allows zero- wait read if the desired data has already been fetched in the FIFO.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
7
8
3
4
5
6
8 cycles
24-bit address
4
3
2
1
0
20
21
22
23
The QSPI treats the dummy cycle as 8 cycles with 1 driving cycle.
(QSPI_nMOD.CHDL[3:0] bits = 0x0, QSPI_nMOD.CHLN[3:0] bits = 0x7)
(3-byte address, 0xeb [ExtAdd = 0], LC = 0b00)
2 cycles
6 cycles
Data N+1
24-bit address
4
0
20
21
5
1
6
2
22
23
7
3
The QSPI treats the dummy cycle as 8 cycles with 1 driving cycle.
(QSPI_nMOD.CHDL[3:0] bits = 0x0, QSPI_nMOD.CHLN[3:0] bits = 0x7)
(3-byte address, LC = 0b00)
Seiko Epson Corporation
12
13
14
15
16
17 18
4 cycles
6 cycles
2 cycles
Dummy
Mode
0
4
0
4
1
5
1
5
2
6
2
6
3
7
3
7
4 cycles
2 cycles
Dummy
Mode
0
4
0
4
1
5
1
5
2
6
2
6
3
7
3
7
19
20
21
22
23
2 cycles
2 cycles
Data 1
Data 2
4
0
4
0
5
1
5
1
6
2
6
2
7
3
7
3
2 cycles
2 cycles
Data 1
Data 2
4
0
4
0
5
1
5
1
6
2
6
2
7
3
7
3
15-11
Advertisement
