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1.8 PROTECTION SCHEME DESCRIPTIONS
1
Figure 1–17: HYBRID LOGIC DIAGRAM on page 1–37 is the logic diagram for the Hybrid scheme. A Hybrid
scheme combines aspects of a tripping scheme with aspects of a blocking scheme, but it is perhaps easiest to
explain as an enhanced POTT scheme.
A pure POTT scheme cannot trip any terminal of the protected line for an internal fault that produces little or no
fault current at one terminal, such that the trip functions there do not operate. A Hybrid scheme incorporates an
echo or repeat transmitter-keying circuit that permits the strong in-feed end(s) to trip. A weak in-feed trip circuit
permits the weak in-feed end to trip almost simultaneously with the strong in-feed end.
A Hybrid scheme requires reverse-looking blocking functions to implement these enhancements and the same
transient blocking logic used in a Blocking scheme. Like a POTT scheme, a Hybrid scheme generally uses a
frequency-shift (FSK) channel.
When an internal fault produces sufficient fault current to operate the tripping functions at each terminal of the
line, the Hybrid scheme operates exactly like the POTT1 scheme described earlier. When a weak- or zero-in-
feed condition exists at one terminal, then the echo keying circuit is used to permit the strong in-feed terminal
to trip. A selectable weak in-feed tripping circuit may be used to trip the weak in-feed terminal.
Assume that an internal fault on the protected line is not detected at a weak in-feed terminal. At the strong in-
feed terminal(s), the transmitter is keyed to the trip frequency. At the weak in-feed terminal, the blocking func-
tions have not operated and the receiver produces an output when it receives the trip frequency. This output is
applied to timer TL11 and AND102 via OR101. AND102 produces an output until timer TL11 times out 80 ms
after receipt of the trip signal. An AND102 output initiates keying of the transmitter via OR404 and AND204.
Transmission (echo) of the trip signal then allows the strong terminal(s) to trip.
C S 6 1 C
('U' LOGIC
O U T P U T )
( S W I T C H E D P O S I T I V E B A T T E R Y )
( S W I T C H E D N E G A T I V E B A T T E R Y )
K E Y
T R A N S M I T T E R
ISOL.
T O T R I P
1-
36
T B 3
S A
9
4
1 0
5
T B 2
T A
8
3
9
2
6
5
7
9
9
6
D C
8
7
Figure 1–16: HYBRID SCHEME INTERCONNECTION WITH CS61C
LPS-D Line Protection System
L P S - D S E T F O R H Y B R I D S C H E M E
PICKSCHEME = 3 (HYBRID)
( + ) B A T T E R Y
S H O W N F O R T H E D E F A U L T
L P S - D I / O A S S I G M E N T S
(-) BATTERY
B 5
K T 1
K E Y T R A N S M I T T E R
B 2 1
I N T E R C O N N E C T D I A G R A M
F O R H Y B R I D S C H E M E
U S I N G C S 6 1 C U N B L O C K I N G C A R R I E R S E T
A N D L P S - D R E L A Y S Y S T E M
1 PRODUCT DESCRIPTION
1.8.7 HYBRID SCHEME
L P S - D
D 2
( R E C E I V E D
C C 1
TRIP SIGNAL)
D 1 8
GE Power Management
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