Epson 6200A Core Cpu Manual page 30

3 INSTRUCTION SET
Operation Mne-
Operand
Code (HEX) monic
E40 to E5F
PSET p
E60 to E6F LDPX MX, i
E70 to E7F
LDPY MY, i
E80 to E83 LD XP, r
E84 to E87
LD XH, r
E88 to E8B LD XL, r
E8C to E8F
RRC r
E90 to E93 LD YP, r
E94 to E97
LD YH, r
E98 to E9B LD YL, r
EA0 to EA3
LD r, XP
EA4 to EA7 LD r, XH
EA8 to EAB
LD r, XL
EB0 to EB3 LD r, YP
EB4 to EB7
LD r, YH
EB8 to EBB LD r, YL
EC0 to ECF
LD r, q
EE0 INC X
EE0 to EEF
LDPX r, q
EF0 INC Y
EF0 to EFF
LDPY r, q
F00 to F0F CP r, q
F10 to F1F
FAN r, q
F28 to F2B ACPX MX, r
F2C to F2F
ACPY MY, r
F38 to F3B SCPX MX, r
F3C to F3F
SCPY MY, r
F40 to F4F SET F, i
F41
SCF
F42
SZF
F44
SDF
F48
EI
F50 to F5F RST F, i
F57
DI
F5B RDF
F5D
RZF
F5E RCF
F60 to F6F Mn
INC
F70 to F7F DEC Mn
F80 to F8F
LD Mn, A
24
Operation Code
B A 9 8 7 6 5 4 3 2
1 1 1 0 0 1 0 p4 p3 p2
1 1 1 0 0 1 1 0 i3 i2
1 1 1 0 0 1 1 1 i3 i2
1 1 1 0 1 0 0 0 0 0
1 1 1 0 1 0 0 0 0 1
1 1 1 0 1 0 0 0 1 0
1 1 1 0 1 0 0 0 1 1
1 1 1 0 1 0 0 1 0 0
1 1 1 0 1 0 0 1 0 1
1 1 1 0 1 0 0 1 1 0
1 1 1 0 1 0 1 0 0 0
1 1 1 0 1 0 1 0 0 1
1 1 1 0 1 0 1 0 1 0
1 1 1 0 1 0 1 1 0 0
1 1 1 0 1 0 1 1 0 1
1 1 1 0 1 0 1 1 1 0
1 1 1 0 1 1 0 0 r1 r0
1 1 1 0 1 1 1 0 0 0
1 1 1 0 1 1 1 0 r1 r0
1 1 1 0 1 1 1 1 0 0
1 1 1 0 1 1 1 1 r1 r0
1 1 1 1 0 0 0 0 r1 r0
1 1 1 1 0 0 0 1 r1 r0
1 1 1 1 0 0 1 0 1 0
1 1 1 1 0 0 1 0 1 1
1 1 1 1 0 0 1 1 1 0
1 1 1 1 0 0 1 1 1 1
1 1 1 1 0 1 0 0 i3 i2
1 1 1 1 0 1 0 0 0 0
1 1 1 1 0 1 0 0 0 0
1 1 1 1 0 1 0 0 0 1
1 1 1 1 0 1 0 0 1 0
1 1 1 1 0 1 0 1 i3 i2
1 1 1 1 0 1 0 1 0 1
1 1 1 1 0 1 0 1 1 0
1 1 1 1 0 1 0 1 1 1
1 1 1 1 0 1 0 1 1 1
1 1 1 1 0 1 1 0 n3 n2
1 1 1 1 0 1 1 1 n3 n2
1 1 1 1 1 0 0 0 n3 n2
Flag
Clock
1 0 I D Z C
p1 p0 5 NBP
i1 i0 5 M(X)
i1 i0 5 M(Y)
r1 r0 5 XP r
r1 r0 5 XH r
r1 r0 5 XL r
r1 r0 5 d3 C, d2
r1 r0 5 YP r
r1 r0 5 YH r
r1 r0 5 YL r
r1 r0 5 r XP
r1 r0 5 r XH
r1 r0 5 r XL
r1 r0 5 r YP
r1 r0 5 r YH
r1 r0 5 r YL
q1 q0 5 r q
0 0 5 X X+1
q1 q0 5 r q, X
0 0 5 Y Y+1
q1 q0 5 r q, Y
q1 q0 7 r-q
q1 q0 7 r q
r1 r0 7 M(X)
r1 r0 7 M(Y)
r1 r0 7 M(X)
r1 r0 7 M(Y)
i1 i0 7 F FVi3~i0
0 1 7 C 1
1 0 Z 1
7
0 0 7 D 1 (Decimal Adjuster ON)
0 0 I 1 (Enables Interrupt)
7
i1 i0 7 F F i3~i0
1 1 I 0 (Disables Interrupt)
7
1 1 7 D 0 (Decimal Adjuster OFF)
Z 0
0 1 7
1 0 7 C 0
M(n3~n0)
n1 n0 7
n1 n0 7 M(n3~n0)
M(n3~n0)
n1 n0 5
EPSON
Operation
p4, NPP p3~p0
i3~i0, X X+1
i3~i0, Y Y+1
d3, d1 d2, d0 d1, C
X+1
Y+1
M(X)+r+C, X X+1
M(Y)+r+C, Y Y+1
M(X)-r-C, X X+1
M(Y)-r-C, Y Y+1
M(n3~n0)+1
M(n3~n0)-1
A
S1C6200/6200A CORE CPU MANUAL
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