Disable Interrupts; Enable Interrupts - Epson 6200A Core Cpu Manual

Core cpu cmos 4-bit single chip microcomputer
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DI
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
EI
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL

Disable interrupts

DI
I
0
1 1 1 1 0 1 0 1 0 1 1 1
MSB
VI
7
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Reset
Disables all interrupts.
C flag
0
Z flag
1
D flag
0
I flag
1

Enable interrupts

EI
I
1
1 1 1 1 0 1 0 0 1 0 0 0
MSB
VI
7
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Set
Enables all interrupts.
C flag
1
Z flag
0
D flag
0
I flag
0
F57H
LSB
DI
0
1
0
0
F48H
LSB
EI
1
0
0
1
EPSON
3 INSTRUCTION SET
39

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