Table of Contents
Advertisement
LD A,Mn
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD B,Mn
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Load memory into A-register
LD A,Mn
A
M(n
to n
)
3
0
1 1 1 1 1 0 1 0 n
MSB
IV
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the contents of the data memory location addressed by Mn into the A-
register.
LD A,M5
A register
0100
Memory (05H)
1111
Memory (06H)
0100
Load memory into B-register
LD B,Mn
B
M(n
to n
)
3
0
1 1 1 1 1 0 1 1 n
MSB
IV
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the contents of the data memory location addressed by Mn into the B-
register.
LD B,M7
B register
0100
Memory (07H)
0110
Memory (08H)
1010
n
n
n
FA0H to FAFH
3
2
1
0
LSB
LD A,M6
1111
0100
1111
1111
0100
0100
n
n
n
FB0H to FBFH
3
2
1
0
LSB
LD B,M8
0110
1010
0110
0110
1010
1010
EPSON
3 INSTRUCTION SET
47
Advertisement
Table of Contents
