Epson 6200A Core Cpu Manual page 62

3 INSTRUCTION SET
LD SPH,r
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD SPL,r
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
56
Load r-register into SPH
LD SPH,r
SPH r
1 1 1 1 1 1 1 0 0 0 r
MSB
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Loads the contents of the r-register into the four high-order bits of the stack
pointer.
LD SPH,A
SPH 1001
A register 0011
Memory (MY) 1100
Load r-register into SPL
LD SPL,r
SPL r
1 1 1 1 1 1 1 1 0 0 r
MSB
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Loads the contents of the r-register into the four low-order bits of the stack pointer.
LD SPL,B
SPL 1011
B register 0111
Memory (MX) 1111
r FE0H to FE3H
1 0
LSB
LD SPH,MY
0011 1100
0011 0011
1100 1100
r FF0H to FF3H
1 0
LSB
LD SPL,MX
0111 1111
0111 0111
1111 1111
EPSON
S1C6200/6200A CORE CPU MANUAL