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SZF
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
XOR r,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Set zero flag
SZF
Z
1
1 1 1 1 0 1 0 0
MSB
VI
7
C –
Not affected
Z –
Set
D –
Not affected
I –
Not affected
Sets the Z (zero) flag.
Z flag
0
Exclusive-OR immediate data i with r-register
XOR r,i
r
r
i
to i
3
0
1 1 0 1 0 0 r
MSB
II
7
C –
Not affected
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Performs an exclusive-OR operation between immediate data i and the contents
of the r-register. The result is stored in the r-register.
XOR A,12
A register
0110
Memory (MX)
0001
Z flag
0
0 0 1 0
LSB
SZF
1
r
i
i
i
i
1
0
3
2
1
0
LSB
XOR MX,1
1010
0001
0
EPSON
3 INSTRUCTION SET
F42H
D00H to D3FH
1010
0000
1
81
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