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3 INSTRUCTION SET
RETS
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
RLC r
Source Format:
Source Format:
Operation:
Operation:
OP-Code:
OP-Code:
Type:
Type:
Clock Cycles:
Clock Cycles:
Flag:
Flag:
Description:
Description:
Example:
Example:
74
Return then skip an instruction
RETS
PCSL
M(SP), PCSH
1 1 1 1 1 1 0 1
MSB
VI
12
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Jumps to the return address that was pushed onto the stack when the subroutine
was called and then skips one instruction.
PCP
0110
PCS
1001 0000
SP
B0
Memory (SP)
0110
Memory (SP+1)
0000
Memory (SP+2)
0000
Rotate r-register left with carry
RLC r
d
d
, d
d
, d
3
2
2
1
1
1 0 1 0 1 1 1 1
MSB
IV
7
C –
Set when the high-order bit of the r-register is 1; otherwise, reset.
Z –
Not affected
D –
Not affected
I –
Not affected
Shifts the contents of the r-register one bit to the left. The high-order bit is shifted
into the carry flag and the carry bit becomes the low-order bit of the r-register.
C
r-register
C
d
d
d
d
3
2
1
0
A register
0011
C flag
1
M(SP+1), PCP
M(SP+2), SP
1 1 1 0
FDEH
LSB
RETS
0000
0000 0111
B3
0110
0000
0000
d
d
C, C
d
0,
0
3
r
r
r
r
AF0H to AFFH
1
0
1
0
LSB
C
r-register
d
d
d
d
3
2
1
0
RLC A
0111
0
EPSON
SP + 3, PC
C
S1C6200/6200A CORE CPU MANUAL
PC + 1
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