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ADC r,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
ADC r,q
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Add with carry immediate data i to r-register
ADC r,i
r
r + i
to i
+ C
3
0
1 1 0 0 0 1 r
MSB
II
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and immediate data i to the r-register.
ADC MX,3
Memory (MX)
0100
B register
1001
C flag
1
Z flag
1
Add with carry q-register to r-register
ADC r,q
r
r + q + C
1 0 1 0 1 0 0 1 r
MSB
IV
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and the contents of the q-register to the r-register.
ADC MY,A
A register
0101
B register
0001
Memory (MX)
0111
Memory (MY)
1011
C flag
1
Z flag
0
r
i
i
i
i
1
0
3
2
1
0
LSB
ADC B,7
1000
1001
0
0
r
q
q
1
0
1
0
LSB
ADC MX,B
0101
0001
0111
0001
1
0
EPSON
3 INSTRUCTION SET
C40H to C7FH
1000
0000
1
1
A90H to A9FH
0101
0001
1001
0001
0
0
29
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