Epson 6200A Core Cpu Manual page 55

Core cpu cmos 4-bit single chip microcomputer
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LDPX MX,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LDPX r,q
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Load immediate data i into MX, increment X by 1
LDPX MX,i
M(X)
i
to i
, X
X + 1
3
0
1 1 1 0 0 1 1 0
MSB
IV
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads immediate data i into the data memory location addressed by IX. X is
incremented by 1. Incrementing X does not affect the flags.
LDPX MX,7
X register
1000 0011
Memory (83H)
0010
Memory (84H)
1001
Load q-register into r-register, increment X by 1
LDPX r,q
r
q, X
X + 1
1 1 1 0 1 1 1 0
MSB
IV
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the contents of the q-register into the r-register. X is incremented by 1.
Incrementing X does not affect the flags.
LDPX A,B
X register
0100 1001
A register
1010
B register
1101
Memory (MY)
0000
i
i
i
i
E60H to E6FH
3
2
1
0
LSB
LDPX MX,0AH
1000 0100
1000 0101
0111
0111
1001
1010
r
r
q
q
EE0H to EEFH
1
0
1
0
LSB
LDPX B,MY
0100 1010
0100 1011
1101
1101
1101
0000
0000
0000
EPSON
3 INSTRUCTION SET
49

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