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3 INSTRUCTION SET
JP Z,s
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LBPX MX,e
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
46
Jump if zero
JP Z,s
PCB
NBP, PCP
NPP, PCS
0 1 1 0 s
s
s
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Jumps to the destination address specified by the 8-bit operand when the zero flag
is set.
SUB A,B
PCB
0
NBP
0
PCP
0101
NPP
0001
PCS
0000 0010
A register
0110
B register
0110
Z flag
0
Load immediate data e to memory, and increment X by 2
LBPX MX,e
M(X)
e
to e
, M(X+1)
3
0
1 0 0 1 e
e
e
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Stores 8-bit immediate data e in two, consecutive 4-bit locations in data memory.
The X-register is incremented by 2. An overflow in X does not affect the flags.
LBPX MX,18H
X register
0001 1110
Memory (1EH)
0010
Memory (1FH)
1111
Memory (20H)
0000
Memory (21H)
0111
s
to s
if Z = 1
7
0
s
s
s
s
s
600H to 6FFH
5
4
3
2
1
0
LSB
PSET 1BH
0
0
0101
0001
0000 0011
0000 0100
0000
0110
1
e
to e
, X
X + 2
7
4
e
e
e
e
e
900H to 9FFH
5
4
3
2
1
0
LSB
LBPX MX,36H
0010 0000
0010 0010
1000
0001
0000
0111
EPSON
JP Z,10H
0
1
1
1
0101
1011
1011
1011
0001 0000
0000
0000
0110
0110
1
1
1000
0001
0110
0011
S1C6200/6200A CORE CPU MANUAL
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