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3 INSTRUCTION SET
ADC XH,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
ADC XL,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
30
Add with carry immediate data i to XH
ADC XH,i
XH
XH + i
to i
+ C
3
0
1 0 1 0 0 0 0 0 i
MSB
IV
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and immediate data i to XH, the four high-order bits of XHL.
ADC XH,2
XH register
1001
C flag
1
Z flag
0
Add with carry immediate data i to XL
ADC XL,i
XL
XL + i
to i
+ C
3
0
1 0 1 0 0 0 0 1 i
MSB
IV
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and immediate data i to XL, the four low-order bits of XHL.
ADC XL,3
XL register
0000
C flag
1
Z flag
1
i
i
i
A00H to A0FH
3
2
1
0
LSB
ADC XH,4
1100
0000
0
0
i
i
i
A10H to A1FH
3
2
1
0
LSB
ADC XL,0EH
0100
0010
0
0
EPSON
1
1
1
0
S1C6200/6200A CORE CPU MANUAL
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