Epson 6200A Core Cpu Manual page 40

Core cpu cmos 4-bit single chip microcomputer
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3 INSTRUCTION SET
CALL s
Source Format:
Source Format:
Operation:
Operation:
OP-Code:
OP-Code:
Type:
Type:
Clock Cycles:
Clock Cycles:
Flag:
Flag:
Description:
Description:
Example:
Example:
CALZ s
Source Format:
Source Format:
Operation:
Operation:
OP-Code:
OP-Code:
Type:
Type:
Clock Cycles:
Clock Cycles:
Flag:
Flag:
Description:
Description:
Example:
Example:
34
Call subroutine
CALL s
M(SP-1)
PCP, M(SP-2)
PCP
NPP, PCS
s
MSB
0 1 0 0 s
s
s
7
6
MSB
I
7
C –
C –
Z –
Not affected
D –
Z –
Not affected
D –
I –
Not affected
I –
Not affected
Pushes the program counter (PCP, PCS) onto the stack as the return address,
then calls the subroutine addressed by NPP and the 8-bit operand.
PSET 06H
PCP
0011
PCS
0010 1100
NPP
0001
SP
C0
Memory (SP-1)
xxxx
Memory (SP-2)
xxxx
Memory (SP-3)
xxxx
Call subroutine at page zero
CALZ s
M(SP-1)
PCP, M(SP-2)
PCP
0, PCS
s
to s
7
MSB
0 1 0 1 s
s
s
7
6
MSB
I
7
C –
C –
Z –
Not affected
D –
Z –
Not affected
D –
I –
Not affected
I –
Not affected
Pushes the program counter (PCP, PCS) onto the stack as the return address,
then calls the subroutine addressed by the 8-bit operand. As NPP is reset to 0H,
only a subroutine in page 0 can be called.
CALZ 10H
PCP
1010
PCS
0010 1110
SP
CA
Memory (SP-1)
xxxx
Memory (SP-2)
xxxx
Memory (SP-3)
xxxx
PCSH, M(SP-3)
to s
7
0
LSB
s
s
s
s
s
400H to 4FFH
5
4
3
2
1
0
LSB
CALL 10H
0011
0010 1100
0001 0000
0110
C0
xxxx
xxxx
xxxx
PCSH, M(SP-3)
0
LSB
s
s
s
s
s
500H to 5FFH
5
4
3
2
1
0
LSB
0000
0001 0000
C7
1010
0010
1111
EPSON
PCSL + 1, SP
SP - 3,
0110
0110
BD
0011
0010
1101
PCSL + 1, SP
SP - 3,
S1C6200/6200A CORE CPU MANUAL

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