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RRC r
Source Format:
Source Format:
Operation:
Operation:
OP-Code:
OP-Code:
Type:
Type:
Clock Cycles:
Clock Cycles:
Flag:
Flag:
Description:
Description:
Example:
Example:
RST F,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Rotate r-register right with carry
RRC r
d
C, d
d
, d
3
2
3
1
1 1 1 0 1 0 0 0
MSB
V
5
C –
Set when the low-order bit of the r-register is 1; otherwise, reset.
Z –
Not affected
D –
Not affected
I –
Not affected
Shifts the contents of the r-register one bit to the right. The low-order bit is shifted
into the carry flag and the carry bit becomes the high-order bit of the r-register.
r-register
C
d
d
d
d
C
3
2
1
0
Memory (MY)
1010
C flag
1
Reset flags using immediate data i
RST F,i
F
F
i
to i
3
0
1 1 1 1 0 1 0 1
MSB
IV
7
C –
Reset if i
is zero; otherwise, not affected.
0
Z –
Reset if i
is zero; otherwise, not affected.
1
D –
Reset if i
is zero; otherwise, not affected.
2
I –
Reset if i
is zero; otherwise, not affected.
3
Performs a logical AND operation between immediate data i and the contents of
the flags. The result is stored in each respective flag.
Flags (I,D,Z,C)
1010
d
, d
d
, C
d
2
0
1
0
1 1 r
r
1
0
LSB
r-register
C
d
d
d
3
2
1
RRC MY
1101
0
i
i
i
i
3
2
1
0
LSB
RST F,2
0010
EPSON
3 INSTRUCTION SET
E8CH to E8FH
C
d
0
F50H to F5FH
75
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