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3 INSTRUCTION SET
FAN r,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
FAN r,q
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
40
Logical AND immediate data i with r-register for flag check
FAN r,i
r
i
to i
3
0
1 1 0 1 1 0 r
MSB
II
7
C –
Not affected
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Performs a logical AND operation between immediate data i and the contents of
the r-register. Only the Z flag is affected. The r-register remains unchanged.
FAN A,7
A register
1000
B register
0100
Memory (MY)
1000
C flag
1
Z flag
0
Logical AND q-register with r-register for flag check
FAN r,q
r
q
1 1 1 1 0 0 0 1 r
MSB
IV
7
C –
Not affected
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Performs a logical AND operation between the contents of the q-register and the
contents of the r-register. Only the Z flag is affected. The registers remains
unchanged.
FAN A,B
A register
1000
B register
1010
Memory (MX)
0101
Memory (MY)
1110
C flag
0
Z flag
0
r
i
i
i
i
1
0
3
2
1
0
LSB
FAN MY,9
1000
0100
1000
1
1
r
q
q
1
0
1
0
LSB
FAN MX,B
1000
1010
0101
1110
0
0
EPSON
D80H to DBFH
FAN B,2
1000
1000
0100
0100
1000
1000
1
1
0
1
F10H to F1FH
FAN A,MY
1000
1000
1010
1010
0101
0101
1110
1110
0
0
1
0
S1C6200/6200A CORE CPU MANUAL
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