Epson 6200A Core Cpu Manual page 68

Core cpu cmos 4-bit single chip microcomputer
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3 INSTRUCTION SET
NOT r
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
OR r,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
62
NOT r-register (one's complement)
NOT r
r
r
1 1 0 1 0 0 r
MSB
II
7
C –
Not affected
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Performs a one's complement operation on the contents of the r-register.
NOT A
A register
1001
Memory (MY)
1111
Z flag
0
Logical OR immediate data i with r-register
OR r,i
r
r
i
to i
3
0
1 1 0 0 1 1 r
MSB
II
7
C –
Not affected
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Performs a logical OR operation between immediate data i and the contents of the
r-register. The result is stored in the r-register.
OR B,5
B register
0100
Memory (MX)
0011
Z flag
0
r
1 1 1 1
1
0
LSB
NOT MY
0110
1111
0
r
i
i
i
i
1
0
3
2
1
0
LSB
OR MX,0BH
0101
0011
0
EPSON
D0FH to D3FH
0110
0000
1
CC0H to CFFH
0101
0111
0
S1C6200/6200A CORE CPU MANUAL

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