Epson 6200A Core Cpu Manual page 82

Core cpu cmos 4-bit single chip microcomputer
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3 INSTRUCTION SET
RZF
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
SBC r,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
76
Reset zero flag
RZF
Z
0
1 1 1 1 0 1 0 1
MSB
VI
7
C –
Not affected
Z –
Reset
D –
Not affected
I –
Not affected
Resets the Z (zero) flag.
ADD A,3
Z flag
0
A register
1101
Subtract with carry immediate data i from r-register
SBC r,i
r
r - i
to i
- C
3
0
1 1 0 1 0 1 r
MSB
II
7
C –
Set if a borrow is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Subtracts the carry flag and immediate data i from the r-register.
SBC A,9
A register
1000
Memory (MY)
1110
C flag
0
Z flag
0
1 1 0 1
LSB
RZF
1
0000
r
i
i
i
i
1
0
3
2
1
0
LSB
SBC MY,0DH
1111
1110
1
0
EPSON
F5DH
0
0000
D40H to D7FH
1111
0000
0
1
S1C6200/6200A CORE CPU MANUAL

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