Epson 6200A Core Cpu Manual page 8

1 DESCRIPTION
2
Data Memory
RAM, Peripheral I/O
(4,096 4-bit words max.)
RP (4)
YHL (8)
XHL (8)
Stack Pointer (8)
Program Counter Block
Micro-Instructions
Instruction Decorder
Instruction Register (12)
12-bit data bus
Program Memory
ROM
(8,192 12-bit words max.)
Fig. 1.1 Block diagram
4-bit address bus
XP (4)
YP (4)
Interrupt
Controller
A (4)
TEMPB (5)
I D Z C
S1C6200 CORE CPU
EPSON
Oscillator
Timing
Generator
B (4)
TEMPA (5)
ALU
S1C6200/6200A CORE CPU MANUAL