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LD Y,e
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD YH,r
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Load immediate data e into Y-register
LD Y,e
YH
e
to e
, YL
e
7
4
3
1 0 0 0 e
e
e
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads 8-bit immediate data e into register Y.
LD Y,E1H
YH register
0001
YL register
1100
Load r-register into YH
LD YH,r
YH
r
1 1 1 0 1 0 0 1 0 1 r
MSB
V
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the contents of the r-register into the four high-order bits of register Y.
LD YH,B
YH register
0000
B register
0110
Memory (MX)
0101
to e
0
e
e
e
e
e
800H to 8FFH
5
4
3
2
1
0
LSB
1110
0001
r
E94H to E97H
1
0
LSB
LD YH,MX
0110
0110
0101
EPSON
3 INSTRUCTION SET
0101
0110
0101
59
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