Epson 6200A Core Cpu Manual page 50

Core cpu cmos 4-bit single chip microcomputer
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3 INSTRUCTION SET
JP C,s
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
JP NC,s
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
44
Jump if carry flag is set
JP C,s
PCB
NBP, PCP
NPP, PCS
0 0 1 0 s
s
s
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Jumps to the destination address specified by the 8-bit operand when the carry
flag is set.
ADD A,8
PCB
0
NBP
0
PCP
0010
NPP
0001
PCS
0011 1100
A register
1000
C flag
0
Jump if not carry
JP NC,s
PCB
NBP, PCP
NPP, PCS
0 0 1 1 s
s
s
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Jumps to the destination address specified by the 8-bit operand when the carry
flag is not set.
PSET 11H
PCB
0
NBP
0
PCP
1001
NPP
0001
PCS
1000 1111
C flag
0
s
to s
if C = 1
7
0
s
s
s
s
s
200H to 2FFH
5
4
3
2
1
0
LSB
PSET 06H
0
0
0010
0001
0011 1101
0011 1110
0000
1
s
to s
if C = 0
7
0
s
s
s
s
s
300H to 3FFH
5
4
3
2
1
0
LSB
JP NC,10H
0
1
1001
0001
1001 0000
0001 0000
0
EPSON
JP C,10H
0
0
0
0
0010
0110
0110
0110
0001 0000
0000
0000
1
1
1
1
0001
0001
0
S1C6200/6200A CORE CPU MANUAL

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