External Interrupt 2 Flag Register (Eif2) - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.4.2

External Interrupt 2 Flag Register (EIF2)

The external interrupt 2 flag register (EIF2) is used to hold the interrupt state by flagging
an interrupt request flag when a level interrupt is detected and then clearing the flag.
■
External Interrupt 2 Flag Register (EIF2)
Address
bit7 bit6
0037
H
: Readable/Writable
R/W
: Unused
: Initial value
Table 11.4-3 Explanation of Functions of Each Bit in External Interrupt 2 Flag Register
bit7
to
bit1
bit0
252
Figure 11.4-3 External Interrupt 2 Flag Register (EIF2)
bit5 bit4 bit3 bit2
IF20
No interrupt request
0
("L" level not detected)
Interrupt request is generated
1
("L" level detected)
(EIF2)
Bit name
Unused bits
IF20:
External interrupt
request flag bit
Initial value
bit1 bit0
IF20 -------0
B
R/W
External interrupt request flag bit
When being read
• Bit value is undefined when being read.
• The written value does not affect other operations.
• When an "L" level signal is input to one of the external
interrupt pins(INT20 to INT27) for which external
interrupt inputs are enabled, this bit is set to "1".
• Writing "0" clears this bit, and writing "1" does not change
this bit state and does not affect other operations.
Note:
The external interrupt enable bits of the external interrupt 2
control register (EIE2:IE20 to IE27) may disable external
interrupt inputs. Interrupt requests continue to be generated
and issued to the CPU until the IF20 bit is cleared to "0".
When being written
This bit is cleared
No change in the bit, does not
affect other operations
Function