Fujitsu F2MC-8L F202RA Hardware Manual page 263

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Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
Circuit 2
Figure 11.3-1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
PDR read
PDR read
(when read-modify-write
is performed)
PDR write
DDR write
PUL read
PUL write
SPL: Pin status setting bit of standby control register (STBC)
Note:
When the ON setting of the pull-up resistor is selected by the pull-up setting register, the pin state will
be "H" level (pull-up state) rather than Hi-Z during stop mode (SPL = 1). During a reset, however, the
pull-up is invalid and the pin remains at Hi-Z.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
Circuit 2
A/D converter
channel select
To A/D
converter's
analog input
INT20, INT21
INT22, INT23
INT24, INT25
INT26, INT27
PDR
Output
latch
DDR
Stop mode
(SPL = 1)
PUL
P00/INT20/AN4
A/D converter
enable bit
P01/INT21/AN5
P02/INT22/AN6
P03/INT23/AN7
From external
interrupt enable
Stop mode
(SPL = 1)
P04/INT24
P05/INT25
P06/INT26
P07/INT27
Pull-up
resistor
P-ch
Pins
P00/INT20/AN4
N-ch
P01/INT21/AN5
P02/INT22/AN6
P03/INT23/AN7
P04/INT24
P05/INT25
P06/INT26
P07/INT27
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