Confirming The Automatic Algorithm Execution State; Hardware Sequence Flags - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 17 FLASH MEMORY
17.4

Confirming the Automatic Algorithm Execution State

Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequence
flags.
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Hardware Sequence Flags

The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, and DQ2. The
functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit exceeded
flag (DQ5), and toggle bit2 flag (DQ2). The hardware sequence flags can therefore be used to confirm that
writing or chip sector erase has been completed or that erase code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the
flash memory after setting of the command sequence (see Table 17.3-1 in Section "17.3 Starting the Flash
Memory Automatic Algorithm "). Table 17.4-1 lists the bit assignments of the hardware sequence flags.
Table 17.4-1 Bit Assignments of Hardware Sequence Flags
Hardware sequence flag
To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags
can be checked or the status can be determined from the RDY bit of the flash memory control status
register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated,
the state returns to the read/reset state. When creating a program, use one of the flags to confirm that
automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read.
In addition, the hardware sequence flags can be used to confirm whether the second or subsequent sector
erase code write is valid. The following sections describe each hardware sequence flag separately. Table
17.4-2 lists the functions of the hardware sequence flags.
Table 17.4-2 Hardware Sequence Flag Functions
Executing
Exceeding
the time limit
362
bit7 bit6
DQ7 DQ6
State
Automatic writing operation
Automatic erasing operation
Automatic writing operation
Automatic erasing operation
bit5 bit4 bit3
DQ5 - -
DQ7 DQ6 DQ5
DQ7 Toggle 0
0 Toggle 0
DQ7 Toggle 1
0 Toggle 1
bit2 bit1 bit0
DQ2 - -
DQ2
1
Toggle
1
Toggle