Fujitsu F2MC-8L F202RA Hardware Manual page 103

Table 4.3-3 lists the functions of port 3 registers.
Table 4.3-3 Functions of Port 3 Registers
Register
Data
name
0
Port 3 data
register
(PDR3)
1
0
Port 3 data
direction
register
(DDR3)
1
R/W : Readable and Writable
W : Write only
X : Undefined
● Port 3 pull-up setting register (PUL3)
The bits of the pull-up setting register correspond to the pins of port 3 in one-to-one correspondence. When
the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level (pull-up
state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up is invalid and the pin
remains at Hi-Z.
Figure 4.3-2 shows the pull-up resistor settings assigned to the values of the bits of the port 3 pull-up
register.
Address
0071 PUL37 PUL36 PUL35 PUL34 PUL33 PUL32 PUL31 PUL30
H
R/W : Readable and Writable
:
When being
When being written
read
Output latch of "0" is set and
Pin state is
"L" level is output to the pin in
"L" level.
output port mode.
Output latch of "1" is set and
Pin state is
"H" level is output to the pin in
"H" level.
output port mode.
Output transistor operation is
disabled and the pin is set to
Read
serve as an input pin.
prohibited
Output transistor operation is
(write only)
enabled and the pin is set to
serve as an output pin.
Figure 4.3-2 Pull-up Setting Register (PUL3)
bit7 bit6 bit5 bit4 bit3
R/W R/W R/W R/W R/W
0
1
0
1
Initial value
bit2 bit1 bit0
Initial value
00000000
R/W R/W R/W
PUL32
PUL33
P32 pull-up OFF
P33 pull-up OFF
P33 pull-up ON
P32 pull-up ON
PUL36
PUL37
P37 pull-up OFF P36 pull-up OFF P35 pull-up OFF P34 pull-up OFF
P37 pull-up ON P36 pull-up ON
CHAPTER 4 I/O PORTS
Read/
Address
Write
R/W 000C XXXXXXXX
H
W 000D
H
B
PUL31 PUL30
P31 pull-up OFF P30 pull-up OFF
P30 pull-up ON
P31 pull-up ON
PUL35 PUL34
P34 pull-up ON
P35 pull-up ON
Initial value
B
00000000
B
87