Serial Status And Data Register (Ssd) - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 13 UART
13.4.3

Serial Status and Data Register (SSD)

The serial status and data register (SSD) controls data transmission/reception of UART
and status in an error, enables/disables interrupts, and specifies and checks settings
for parity or bit-8 transmitting data.
■
Serial Status and Data Register (SSD)
Address bit7
002A
RDRF ORFE TDRE
H
: Readable/Writable
R/W
R : Read only
: Unused
X : Undefined
: Initial value
* : Effective only when data length is 9 bits (SMC: MC1 and MC0 = 10
294
Figure 13.4-4 Serial Status and Data Register (SSD)
bit6 bit5 bit4 bit3
TIE RIE
R R R/W R/W R/W
RD8/
RP
0
1
TD8/
TP
0
1
RIE
0
1
TIE
0
1
TDRE
0
1
RDRF ORFE
0
0
1
1
bit2 bit1 bit0
Initial value
00100-1X
TD8/TP RD8/RP
B
R/W R
Bit-8 receiving data/parity bit
Parity used
(SMC: PEN = 1)
Detects odd parity.
Detects even parity.
Bit-8 transmitting data/parity bit
Parity used
(SMC: PEN = 1)
Adds odd parity.
Adds even parity.
Reception interrupt request enable bit
Disables output of reception interrupt requests.
Enables output of reception interrupt requests.
Transmission interrupt request enable bit
Disables output of transmission interrupt requests.
Enables output of transmission interrupt requests.
Transmitted data flag bit
Data to be transmitted included
Data to be transmitted not included
Received data flag bit/Overrun/Framing error flag bit
No data
0
1 Framing error
0
Normal data
1
Overrun error (previous data remaining)
and 11
B
Parity not used
(SMC: PEN = 0)
Bit-8 receiving data*
Parity not used
(SMC: PEN = 0)
Sets bit-8 transmitting data.*
, operating mode is 2 or 3.)
B