Fujitsu F2MC-8L F202RA Hardware Manual page 206

CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● Detection of the number of events
In the external clock mode, counter clear can be prohibited by the compare match counter clear mask bit
(TCMSK) of the capture control register (TCCR) when a match is detected. Setting the compare match
counter clear mask bit to "1" enables the event count detection function to be used. In this case, a compare
match does not cause data to be re-loaded to the compare latch. To update the compare latch value, stop
and restart the timer.
Figure 8.7-2 shows counter function operation in the external clock mode in which TCMSK is used.
Figure 8.7-2 Counter Function Operation in External Clock Mode
EC
TSTR0=1
TDR0
TCMSK=0
Compare latch
Counter clear
Un-
Counter value
defined
TCMSK=1
Compare latch
Counter clear
Un-
Counter value
defined
TIF0
190
7F
H
00 00 01
H H
00 00 01
H H
FF
7F
H
02 03 7E
H H
7F
02 03 7E
H H
H
7F 00
H H H
7F 80
H H H
TFCR0=1
55
H
FF
H
01
H
81
H
(W)