Timer 1 Control Register (Tcr1) - Fujitsu F2MC-8L F202RA Hardware Manual

8.4.3

Timer 1 Control Register (TCR1)

The timer 1 control register (TCR1) is used to select functions, allow and prohibit
operation, control interrupts, and check interrupt states in timer 1 for the 8-bit mode of
the 8/16-bit capture timer/counter. When used in the 16-bit mode, TCR1 is controlled by
the timer 0 control register (TCR0), but TCR1 setting is required.
■
Timer 1 Control Register (TCR1)
Address
bit7
001A TIF1 TFCR1 T1IEN
H
R
R/W : Readable/Writable
R : Read only
: Initial value
Figure 8.4-4 Timer 1 Control Register (TCR1)
bit6 bit5 bit4 bit3 bit2
TCS12 TCS11 TCS10 TSTR1
R/W R/W R/W R/W
TSTR1
0
1
TCS12 TCS11 TCS10
0
0
0
0
1
1
1
1
t : Instruction cycle (Affected by the clock mode and others.)
INST
T1IEN
0
1
TFCR1
0
1
TIF1
0
1
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
bit1 bit0
Initial value
000-0000
B
R/W R/W
Timer start bit
The counter operation is stopped.
The counter is cleared and increment is started.
Clock source selection bits (oscillation: 12.5 MHz)
0 0
2t
INST
0 1
4t
INST
1 0
16t
INST
1 1 64t
INST
0 0 128t
INST
256t
0 1
INST
512t
1 0
INST
16-bit mode
1 1
Interrupt request enable bit
Interrupt request output is prohibited.
Interrupt request output is allowed.
Compare match detection flag clear bit
Not affected (at read, always "0")
The compare match detection flag is cleared.
Compare match detection flag bit
A compare match has not occurred.
A compare match has occurred.
[0.64 µs]
[1.28 µs]
[5.12 µs]
[20.48 µs]
[40.96 µs]
[81.92 µs]
[163.84 µs]
175