Fujitsu F2MC-8L F202RA Hardware Manual page 97

Table 4.2-3 lists the functions of the port 0 registers.
Table 4.2-3 Functions of Port 0 Registers
Register
Data
name
0
Port 0 data
register (PDR0)
1
0
Port 0 data
direction
register (DDR0)
1
R/W : Readable/Writable
W : Write only
X : Undefined
● Port 0 pull-up setting register (PUL0)
The bits of the pull-up setting register correspond to the pins of port 0 in one-to-one correspondence. When
the pull-up resistor is selected by using the pull-up setting register, the pin will be at "H" level (pull-up
state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up is invalid and the pin
remains at Hi-Z.
Figure 4.2-2 shows the pull-up resistor settings assigned to the values of the bits of the port 0 pull-up
register.
Address
0070
PUL07 PUL06 PUL05 PUL04 PUL03 PUL02 PUL01 PUL00
H
R/W
: Readable/Writable
: Initial value
When being
When being written
read
Output latch of "0" is set and
Pin state is
"L" level is output to the pin
"L" level.
in output port mode.
Output latch of "1" is set and
Pin state is
"H" level is output to the pin
"H" level.
in output port mode.
Output transistor operation
is disabled and the pin is set
Read
to serve as an input pin.
prohibited
Output transistor operation
(write only)
is enabled and the pin is set
to serve as output pin.
Figure 4.2-2 Pull-up Resistor Settings (PUL0)
bit7 bit6 bit5 bit4 bit3
R/W R/W R/W R/W R/W
0
1
0
1
Initial value
bit2 bit1 bit0
00000000
R/W R/W R/W
PUL02
PUL03
P03 pull-up OFF
P02 pull-up OFF
P03 pull-up ON P02 pull-up ON
PUL07 PUL06
P07 pull-up OFF P06 pull-up OFF
P07 pull-up ON P06 pull-up ON
CHAPTER 4 I/O PORTS
Read/
Address
Write
R/W 0000 XXXXXXXX
H
W 0001
H
B
PUL00
PUL01
P01 pull-up OFF P00 pull-up OFF
P01 pull-up ON P00 pull-up ON
PUL04
PUL05
P05 pull-up OFF P04 pull-up OFF
P05 pull-up ON P04 pull-up ON
Initial value
B
00000000
B
81