Fujitsu F2MC-8L F202RA Hardware Manual page 299

Table 13.1-4 provides an example of the baud rates selectable when the 8-bit PWM timer is used.
Table 13.1-4 Transfer Cycles and Transfer Rates Selectable for the 8-bit PWM Timer
PWM timer
count clock
cycle Divider for clock
CR=0
1t
INST
CR=1
CR=0
16t
INST
CR=1
CR=0
64t
INST
CR=1
CR=0
8/16-bit capture
timer/counter
CR=1
t : Instruction cycle
INST
The system clock control register (SYCC) selects the maximum clock speed (CS1 and CS0 = 11
4/F ) in active mode.
CH
Figure 13.1-4 shows an example of calculating the baud rate when the PWM timer is selected.
Figure 13.1-4 Example of Calculating the Baud Rate (when the PWM Timer is Selected)
1
Value of baud rate
The value of the baud rate is determined by the clock input specified in the clock dividing rate register
(CS1 and CS0). The clock input is determined with an external clock (PWM timer). For calculation, see
Table 13.1-3 and Table 13.1-4 .
• When an external clock is selected (F
1/49kbps=1.28 µs (min.) × 16 (CR=0)
• When the PWM timer is selected (F
1/98kbps=0.32 µs (4/F
1/24414 bps=0.32 µs (4/F
Asynchronous transfer mode
Transfer rate (bps)
16 97656 to 763
64 24414 to 191
16 6103 to 47.8
64 1526 to 11.9
16 1526 to 11.9
64 381.5 to 3
16 48828 to 381.5
64 12207 to 95.4
Clock gear
Input clock select bit
selected (PWM)
1(P1=0,P0=0)
64/F
CH
16/F 16(P1=0,P0=1)
CH
=
8/F
64(P1=1,P0=0)
CH
4/F 8/16 timer (P1=1,P0=1)
CH
) × 1 (P1=0,P0=0) × 1 (COMR=0) × 2 × 16 (CR=0)
CH
) × 1 (P1=0,P0=0) × 1 (COMR=0) × 2 × 64 (CR=1)
CH
Divider for
clock
Compare register
(COMP)
Value specified in the
compare register + 1
= 12.5 MHz)
CH
= 12.5 MHz)
CH
CHAPTER 13 UART
Synchronous transfer mode
Transfer rate (bps)
2 781k to 6.1k
2 48828 to 381.5
2 12207 to 95.4
2 391k to 3k
, 1 instruction cycle =
B
CR=0:16
2 CR
CR=1:64
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