Interrupt Of A/D Converter - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 12 A/D CONVERTER
12.5

Interrupt of A/D Converter

A factor for an interrupt of the A/D converter is the following.
• Completion of conversion when A/D conversion functions are enabled
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Interrupt when A/D Conversion Functions are Enabled
When A/D conversion is completed, the interrupt request flag bit (ADC1: ADI) is set to "1". At this time, if
the bit for enabling an interrupt request is enabled (ADC2: ADIE = 1), an interrupt request to the CPU
(IRQ8) occurs. Write "0" to the ADI bit using the routine for interrupt handling to clear the interrupt
request.
The ADI bit is set when A/D conversion is completed, irrespective of the value of the ADIE bit.
Note:
When the ADI bit is "1", if the ADIE bit is enabled (changed from "0" to "1"), an interrupt request
occurs immediately.
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Register and Vector Table Related to the Interrupt of the A/D Converter
Table 12.5-1 Register and Vector Table Related to the Interrupt of the A/D Converter
Interrupt name
IRQ8
See Section "3.4.2 Steps in the Interrupt Operation " for the interrupt operation.
272
Register to set the interrupt level
Register
ILR3 (007D )
L81 (bit1)
H
Bit to be set
L80 (bit0)
Address of the vector table
High order Low order
FFEA FFEB
H H