Fujitsu F2MC-8L F202RA Hardware Manual page 101

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Block Diagram of Port 3
PDR read
PDR read
(when read-modify-write is
performed)
PDR write
DDR write
PUL read
PUL write
Note:
Because the value states of the pins are always input to the external interrupt circuit, when a pin is used
as a normal I/O port, the operation of the external interrupt circuit corresponding to the pin must be
inhibited. See "CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) ".
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Registers PDR3, DDR3, and PUL3 of Port 3
The registers PDR3, DDR3, and PUL3 are associated with port 3.
The bits of these registers correspond to the pins of port 3 in one-to-one correspondence.
Table 4.3-2 tabulates the correspondence between the pins and the bits of port 3 registers.
Table 4.3-2 Correspondence between the Pins and the Bits of Port 3 Registers
Port name
PDR3, DDR3, PUL3
Port 3
Pin corresponding to bit
Figure 4.3-1 Block Diagram of Port 3
External
interrupt
Input to
peripheral
Input to
PDR
peripheral
Output from peripheral
Output latch
DDR
Stop mode
(SPL = 1)
PUL
Bits of associated registers and corresponding pins
bit7
P37
External interrupt
enable
Stop mode
(SPL = 1)
Output
Output occurring
from
peripheral
from peripheral
enable
Pch
Nch
bit6 bit5 bit4
P36 P35 P34
CHAPTER 4 I/O PORTS
External interrupt
occurring
Hysteresis input
CMOS input
Pull-up resistor
Pins
bit3 bit2 bit1
P33 P32 P31
bit0
P30
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