Interrupt Level Setting Registers (Ilr1 To Ilr4) - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 3 CPU
3.4.1

Interrupt Level Setting Registers (ILR1 to ILR4)

For the interrupt level setting registers (ILR1, 2, 3, and 4), 16 two-bit data items
corresponding to interrupt requests sent from peripheral functions are assigned.
Interrupt levels can be specified in these 2-bits (interrupt level setting bits).
■
Configuration of the Interrupt Level Setting Registers (ILR1 to ILR4)
Register Address
ILR1
ILR2
ILR3
ILR4
W: Write only
For each interrupt request, 2 bits of the interrupt level setting registers are assigned. The values specified in
the interrupt level setting registers are the intensities for processing the interrupts (interrupt levels 1 to 3).
Interrupt level setting bits are compared with interrupt level bits in the condition code register (CCR: IL1
and IL0).
When interrupt level 3 is specified, the CPU does not accept interrupt requests.
Table 3.4-2 provides the relationship between interrupt level setting bits and interrupt levels.
Table 3.4-2 Relationship between Interrupt Level Setting Bits and Interrupt Levels
L01 to LF1 L00 to LF0
0
0
1
1
Notes:
• When the main program is being executed, the interrupt level bits in the condition code register
(CCR: IL1 and IL0) are normally set to 11
• The ILR1 to ILR4 registers are write-only enabled, and thus the bit manipulation instructions (SETB
and CLRB) cannot be used.
36
Figure 3.4-1 Configuration of Interrupt Level Setting Register
bit7 bit6
007B L31 L30
H
(W) (W)
007C L71 L70
H
(W) (W)
007D LB1 LB0
H
(W) (W)
007E LF1 LF0
H
(W) (W)
Requested interrupt level
0
1
0
1
bit5 bit4 bit3 bit2 bit1
L21 L20 L11 L10 L01
(W) (W) (W) (W) (W)
L61 L60 L51 L50 L41
(W) (W) (W) (W) (W)
LA1 LA0 L91 L90 L81
(W) (W) (W) (W) (W)
LE1 LE0 LD1 LD0 LC1
(W) (W) (W) (W) (W)
1
2
3
.
B
bit0 (Initial value)
L00 1111 1111
B
(W)
L40 1111 1111
B
(W)
L80 1111 1111
B
(W)
LC0 1111 1111
B
(W)
Priority
High
Low (no interrupt)