Operation At Serial Output Completion - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 14 8-BIT SERIAL I/O
● Serial output operation using external shift clock
Serial output operation with the external shift clock requires the settings shown in Figure 14.6-2 .
Figure 14.6-2 Settings Required for Serial Output Operation using External Shift Clock
When serial output operation is allowed, the contents of the SDR are output to the SO pin in synchronization
with the falling edge of the external shift clock. When serial operation is completed, immediately reset the SDR,
set it again, then allow serial output operation (SMR: SST = 1) to prepare for the output of the next data.
When the remote serial input operation (rising edge) is completed and the 8-bit serial I/O enters the idle
state (state in which it waits for the output of the next data), set the external shift clock to a high level.
Figure 14.6-3 shows 8-bit serial output operation.
For LSB first
Serial output data
Shift clock
SIOF bit
SST bit
■

Operation at Serial Output Completion

At the rising edge of the shift clock for serial data of the 8th bit, the interrupt request flag bit (SMR: SIOF)
is set to "1" and the serial I/O start bit (SMR: SST) is set (cleared) to "0".
326
bit7
bit6
SMR SIOF SIOE
SDR
DDR3
SSEL
: Used bit
: Unused bit
: Set "0"
0
1
: Set "1"
Figure 14.6-3 8-bit Serial Output Operation
bit7 bit6 bit5
SDR #7 #6 #5
#0 #1
0 1
Transfer start
bit5 bit4 bit3 bit2
SCKE SOE CKS1 CKS0
0 1 1 1
Transmission data setting
bit4 bit3 bit2 bit1
#4 #3 #2 #1
#2 #3 #4
2 3 4 5
bit1 bit0
BDS SST
1
0
SSEL
1
bit0
SO pin
#0
#5 #6 #7
Clear via program
6 7
Interrupt request
Automatic clear at transfer end