Fujitsu F2MC-8L F202RA Hardware Manual page 62

CHAPTER 3 CPU
Table 3.5-3 Explanation of Functions of Each Bit in the Reset Flag Register (RSFR)
bit7
bit6
bit5
bit4
bit3
to
bit0
Note:
A reset source flag is set when a reset source is generated. When the reset source flag register is read, all
bits in the reset source flag register are cleared. Therefore, to determine the source of a reset, read this
register using the initial value setting routine after the reset.
46
Bit name
"1" is set to this bit when power-on reset occurs.
PONR:
"1" is set to this bit after power is turned on.
Power-on reset flag
This bit is cleared with "0" after being read.
bit
Writing a value to this bit has no significance.
"1" is set to this bit when external reset occurs.
"1" is set to this bit while other reset flags are maintained when all
ERST:
other reset flags have been set before the external reset flag is set.
External reset flag bit
This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
"1" is set to this bit when watchdog reset occurs.
WDOG: "1" is set to this bit while other reset flags are maintained when all
Watchdog reset flag other reset flags have been set before the watchdog reset flag is set.
bit This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
"1" is set to this bit when software reset occurs.
SFTR: "1" is set to this bit while other reset flags are maintained when all
Software reset flag other reset flags have been set before the software reset flag is set.
bit This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
The values read out are undefined.
Unused bits
Writing data to these bits does not affect operations.
Description